A Configurable IP for Mode Decision of H.264/AVC Encoder

Authors:
Shih-Chang Hsia;Si-Hong Wang;Ying- Chao Chou
Affiliations:
National Kaohsiung First University of Science and Technology, Taiwan;National Kaohsiung First University of Science and Technology, Taiwan;National Kaohsiung First University of Science and Technology, Taiwan
Venue:
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
Year:
2007

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A 140-MHz 94 K gates HD1080p 30-frames/s intra-only profile H.264 encoder

IEEE Transactions on Circuits and Systems for Video Technology

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Abstract

In this paper, we present a configurable IP for the mode decision in intra predictor of H.264 system. The parallel architecture with three computational cores is proposed by using configurable structure to process YUV pixels, where the number of pixel parallelism is 10 in the output. A commonly hardware is used to computed various coding modes by arranging an efficient schedule for YUV Plane modes computing. The configurable circuit is controlled with multiplex to compute mode parameters to reduce the hardware cost. The luminance with 4x4 and 16x16 block mode and chrominance with 8x8 block mode can be finished during 256 cycles for one MB coding. The throughput rate is about 4~5 times compared to the previous works, and the proposed architecture can meet the speed requirement for 1920*1080/50Hz HDTV encoder.