Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm

Authors:
Esra Sahin;Ilker Hamzaoglu
Affiliations:
Sabanci University, Istanbul, Turkey;Sabanci University, Istanbul, Turkey
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

Citing 2
Cited 3

Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

IEEE Transactions on Circuits and Systems for Video Technology

Exploration of hardware sharing for image encoders

Proceedings of the Conference on Design, Automation and Test in Europe
A parallel approach for high performance hardware design of intra prediction in H.264/AVC video codec

Proceedings of the Conference on Design, Automation and Test in Europe
Computation and power reduction techniques for H.264 intra prediction

Microprocessors & Microsystems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present an efficient hardware architecture for real-time implementation of intra prediction algorithm used in H.264 / MPEG4 Part 10 video coding standard. The hardware design is based on a novel organization of the intra prediction equations. This hardware is designed to be used as part of a complete H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 90 MHz in a Xilinx Virtex II FPGA. The FPGA implementation can process 27 VGA frames (640x480) per second.