Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder
IEEE Transactions on Circuits and Systems for Video Technology
Methods for Power/Throughput/Area Optimization of H.264/AVC Decoding
Journal of Signal Processing Systems
Low-power baseband processing for wireless multimedia systems using unequal error protection
WTS'10 Proceedings of the 9th conference on Wireless telecommunications symposium
Low-power bitstream-residual decoder for H.264/AVC baseline profile decoding
EURASIP Journal on Embedded Systems
Practical design space exploration of an h264 decoder for handheld devices using a virtual platform
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems
ACM Transactions on Embedded Computing Systems (TECS)
| Hi-index | 0.00 |
In this paper, we propose a low-power H.264/AVC baseline decoder. A systematic methodology for power reduction at all design levels for video decoding is proposed and applied. Power consumption is optimized at algorithm, architecture, circuit, and physical levels. The VLSI implementation results show that with UMC 180nm technology, the proposed design is able to decode QCIF 30fps at 1.5MHz. It consumes 698μW operated under 1.8V power supply. The decoder contains 169k logic gates and 2.5KB on-chip SRAM. The total chip area is 4.4x4.4mm2 in a CQFP 208 package. The low-power and real-time features make our design ideal for portable applications where video quality is often traded off for energy.