A low power variable length decoder for MPEG-2 based on nonuniform fine-grain table partitioning
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware architecture design of an H.264/AVC video codec
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A low power VLSI implementation for variable length decoder in MPEG-1 layer III
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
Low-power H.264/AVC baseline decoder for portable applications
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Priority-based heading one detector in H.264/AVC decoding
EURASIP Journal on Embedded Systems
A power-efficient and self-adaptive prediction engine for H.264/AVC decoding
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and bus-arbitration schemes for MPEG-2 video decoder
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Low-complexity transform and quantization in H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
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We present the design and VLSI implementation of a novel low-power bitstream-residual decoder for H.264/AVC baseline profile. It comprises a syntax parser, a parameter decoder, and an Inverse Quantization Inverse Transform (IQIT) decoder. The syntax parser detects and decodes each incoming codeword in the bitstream under the control of a hierarchical Finite State Machine (FSM); the IQIT decoder performs inverse transform and quantization with pipelining and parallelism. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, TAG method, zero-block skipping, and clock gating, are adopted and integrated throughout the bitstream-residual decoder. With innovative architecture, the proposed design is able to decode QCIF video sequences of 30 fps at a clock rate as low as 1.5 MHz. A prototype H.264/AVC baseline decoding chip utilizing the proposed decoder is fabricated in UMC 0.18µm 1P6M CMOS technology. The proposed design is measured under 1 V ∼ 1.8 V supply with 0.1 V step. It dissipates 76µW at 1 V and 253µW at 1.8 V.