An efficient architecture for H.264 intra prediction mode decision algorithm

Authors:
P. Muralidha;R. Vasundhara Devi;C. B. Rama Rao;N. S. Murthy
Affiliations:
Department of Electronics & Communication Engineering, National Institute of Technology, Warangal, India;Department of Electronics & Communication Engineering, National Institute of Technology, Warangal, India;Department of Electronics & Communication Engineering, National Institute of Technology, Warangal, India;Department of Electronics & Communication Engineering, National Institute of Technology, Warangal, India
Venue:
NEHIPISIC'11 Proceeding of 10th WSEAS international conference on electronics, hardware, wireless and optical communications, and 10th WSEAS international conference on signal processing, robotics and automation, and 3rd WSEAS international conference on nanotechnology, and 2nd WSEAS international conference on Plasma-fusion-nuclear physics
Year:
2011

Citing 2
Cited 0

Overview of the H.264/AVC video coding standard

IEEE Transactions on Circuits and Systems for Video Technology
Analysis, fast algorithm, and VLSI architecture design for H.264/AVC intra frame coder

IEEE Transactions on Circuits and Systems for Video Technology

Quantified Score

Hi-index	0.00

Visualization

Abstract

The paper presents an intra prediction hardware architecture where it exploits parallelism in predicting the pixels and pipelining is implemented during the calculation of the cost function. The parallelism feature includes an optimized data path which calculates only 24 unique pixel values and the former are assigned to the current macro block depending on the equations for different modes as defined in the H.264 standard. Synthesis results confirmed that the proposed architecture is able to process SD 1280×720P @ 50 fps when operating at 57 MHz for ASIC platforms.