FinFETs for nanoscale CMOS digital integrated circuits

Authors:
Tsu-Jae King
Affiliations:
Adv. Technol. Group, Synopsys, Inc., Mountain View, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

Citing 0
Cited 5

Low-power FinFET circuit synthesis using multiple supply and threshold voltages

ACM Journal on Emerging Technologies in Computing Systems (JETC)
FinFET-based dynamic power management of on-chip interconnection networks through adaptive back-gate biasing

ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells

Proceedings of the great lakes symposium on VLSI
Bias optimization of 2.4 GHz double gate MOSFET RF mixer

Analog Integrated Circuits and Signal Processing

Quantified Score

Hi-index	0.00

Visualization

Abstract

Suppression of leakage current and reduction in device-to-device variability are key challenges for sub-45nm CMOS technologies. Nonclassical transistor structures such as the FinFET are likely necessary to meet transistor performance requirements in the sub-20nm gate length regime. This paper presents an overview of FinFET technology and describes how it can be used to improve the performance, standby power consumption, and variability in nanoscale-CMOS digital ICs.