Let caches decay: reducing leakage energy via exploitation of cache generational behavior
ACM Transactions on Computer Systems (TOCS)
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Proceedings of the 43rd annual Design Automation Conference
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Optimizing finfet technology for high-speed and low-power design
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
The effect of process variation on device temperature in FinFET circuits
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Evaluation of multiple supply and threshold voltages for low-power FinFET circuit synthesis
NANOARCH '08 Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures
FinFETs and Other Multi-Gate Transistors
FinFETs and Other Multi-Gate Transistors
Multiscale thermal analysis for nanometer-scale integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Low-power FinFET circuit synthesis using surface orientation optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Gated-diode FinFET DRAMs: Device and circuit design-considerations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 48th Design Automation Conference
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Integration of cache on-chip has significantly improved the performance of modern processors. The relentless demand for ever-increasing performance has led to the need to increase the cache capacity and number of cache levels. However, the performance improvement is accompanied by an increase in chip's power dissipation, requiring the use of more expensive cooling technologies to ensure chip reliability and long product life. The emergence of FinFETs as the technology of choice for high-performance computing poses new challenges to processor designers. With the introduction of new features in FinFETs, for example, independently controllable back gates, researchers have proposed several innovative memory cells that can reduce leakage power significantly, making the integration of a larger cache more practical. In this article, we comprehensively evaluate and compare the performance, power consumption (both dynamic and leakage), area, and temperature of different FinFET SRAM caches by exploring common configurations with varying cache size, block size, associativity, and number of banks. We evaluate caches based on four well-known FinFET SRAM cells: Pass-Gate FeedBack (PGFB), Row-based Back-Gate Biasing (RBGB), 8T, and 4T. We show how the caches can be simulated at self-consistent temperatures (at which leakage and temperature are in equilibrium). Drowsy and decay caches are two well-known leakage reduction techniques. We implement them in the context of FinFET caches to investigate their impact. We show that the RBGB cell-based cache is far superior in leakage and Power-Delay Product (PDP) to those based on the other three cells, sometimes by an order of magnitude. This superiority is maintained even when drowsy or decay leakage reduction techniques are applied to caches based on the other three cells, but not to the one based on the RBGB cell. This significantly diminishes the importance of drowsy or decay cache techniques, at least when the RBGB cell is used.