Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip analysis of leakage power under process variations, including spatial correlations
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2009 International Conference on Computer-Aided Design
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Double-gate CMOS is projected to replace classical bulk and SOI technologies around the 32nm node. Predicting the impact of process variations on yield for these novel devices is necessary at an early stage of the design cycle, to enable optimal technology and circuit design choices. This paper presents a fully physical model for double-gate leakage distribution due to gate length (L) and body thickness (tsi) variations, both for single devices and stacks. The model is derived directly from the solution of Poisson's and Schrödinger's equations, and thus captures the effect of unique double-gate phenomena such as volume inversion and quantum confinement. It is scalable to L=13nm and tsi=3nm, with less than 2% error for 3 σ variation as large as 20% of nominal process parameters.