Variability analysis of FinFET-based devices and circuits considering electrical confinement and width quantization

Authors:
Seid Hadi Rasouli;Kazuhiko Endo;Kaustav Banerjee
Affiliations:
University of California, Santa Barbara, CA;Advanced Industrial Science and Technology, Tsukuba, Ibaraki, Japan;University of California, Santa Barbara, CA
Venue:
Proceedings of the 2009 International Conference on Computer-Aided Design
Year:
2009

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Abstract

FinFET is considered as the most likely candidate to substitute bulk CMOS technology. FinFET-based design, however, requires special attention due to its exclusive properties such as width quantization and electrical confinement (quantum-mechanical effect) even in subthreshold regime. Considering these exclusive properties of FinFETs, the sources of process variations and their effects on FinFET-based circuit characteristics can be significantly different from that in bulk CMOS devices. This paper identifies a new source of random process variation due to the gate work-function variation and resulting electrical confinement in emerging high-k/metal-gate FinFET devices. In order to capture the effect of the variations on the characteristics of multifin FinFETs (considering their width quantization property), this paper also presents a new statistical framework to accurately predict the effective threshold voltage of multifin FinFET devices. This framework is subsequently used to predict the leakage profile of FinFET-based SRAM cells. Since FinFETs are optimal for ultra-low-voltage operations due to near-ideal subthreshold swing (60 mV/dec), we focus on FinFET-based SRAM (including subthreshold SRAM) design. Contrary to the low sensitivity of the static noise margin (SNM) to the width of the pull-down devices in bulk-CMOS subthreshold SRAMs, our analysis shows, for the first time, the significant impact of employing multifin pull-down devices on the SNM of subthreshold FinFET SRAMs.