A High-Performance, Low Leakage, and Stable SRAM Row-Based Back-Gate Biasing Scheme in FinFET Technology

Authors:
Rajiv V. Joshi;Keunwoo Kim;Richard Q. Williams;Edward J. Nowak;Ching-Te Chuang
Affiliations:
IBM T. J. Watson Research Center, Yorktown Heights, NY;IBM T. J. Watson Research Center, Yorktown Heights, NY;IBM Technology Group, Essex Junction, VT 05452, U. S. A;IBM Technology Group, Essex Junction, VT 05452, U. S. A;IBM T. J. Watson Research Center, Yorktown Heights, NY
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

This paper describes back-gate biasing scheme using independent-gate controlled asymmetrical (n+/p+ polysilicon gates) FinFETs devices and its applications to 6-T and 8-T SRAM. Row-based above-VDD/below- GND bias is applied to the back-gates of the access and pull-down cell nFETs to enhance the Read/Write performance, reduce standby leakage, and mitigate process (VT) variability. The application of the technique to stacked Read transistors in 8-T SRAM is also discussed.