A delay model for logic synthesis of continuously-sized networks
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Robust SAT-Based Search Algorithm for Leakage Power Reduction
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Proceedings of the 40th annual Design Automation Conference
Discrete drive selection for continuous sizing
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
FinFET SRAM " Device and Circuit Design Considerations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Convex Optimization
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
New Generation of Predictive Technology Model for Sub-45nm Design Exploration
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Comparative evaluation of layout density in 3T, 4T, and MT FinFET standard cells
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FinFET-Based Power Management for Improved DPA Resistance with Low Overhead
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermal Characterization of Test Techniques for FinFET and 3D Integrated Circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
| Hi-index | 0.00 |
FinFET devices promise to replace traditional MOSFETs because of superior ability in controlling leakage and minimizing short channel effects while delivering a strong drive current. We investigate in this paper gate sizing of finFET devices, and we provide a comparison with 32nm bulk CMOS. Wider finFET devices are built utilizing multiple parallel fins between the source and drain. Independent gating of the finFET's double gates allows significant reduction in leakage current. We perform temperature-aware circuit optimization by modeling delay using temperature-dependent parameters, and by imposing constraints that limit the maximum allowable number of parallel fins. We show that finFET circuits are superior in performance and produce less static power when compared to 32nm circuits.