Logical and physical design: a flow perspective
Logic Synthesis and Verification
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
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Due to deep sub micron effects, accurate gate sizing is increasingly important. Most advanced methods for sizing assume that gates can be sized continuously, while most design is done with discrete gate array and standard cell libraries. To bridge this gap, this paper proposes a new approach to gate sizing which combines a small number of discrete gate sizes to approximate the ideal of continuous sizing. To date research has focussed on deciding an appropriate set of logic functions for the primitive gates in a library. The main contribution of this paper is the development of a theoretical framework for strategies of drive strength selection for libraries. We demonstrate that nearly continuous sizing can be achieved by combining gates of a small number of sizes. The experimental procedure is based on simulated annealing. The results show that with only 5 discrete sizes any continuous size within a range of two orders of magnitude can be approximated with an accuracy of 1.7%.