Double-gate SOI devices for low-power and high-performance applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
ICCS '07 Proceedings of the 7th international conference on Computational Science, Part IV: ICCS 2007
Pragmatic design of gated-diode FinFET DRAMs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Gated-diode FinFET DRAMs: Device and circuit design-considerations
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Hi-index | 0.01 |
The quasi-planar double-gate FinFET has emerged as one of the most likely successors to the classical planar MOSFET for ultimate scalability. Unlike planar devices, its channel width is in the vertical direction; hence it is possible to increase effective channel width (and hence drive current) per unit planar area by increasing fin-height (SOI thickness). This translates directly to improved performance in interconnect-dominated circuits. In this paper, we explore the joint Vdd-fin-height-Vt design space for a 65nm FinFET SRAM. We report that 69% taller fins can accommodate 18% (140mV) lower Vdd as well as 35% (70mV) higher Vt to deliver iso-performance at 87% lower sub-threshold leakage, 50% lower gate leakage, 25% lower dynamic energy, 13% higher static noise margin and 38% higher critical charge for soft-error immunity.