Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
Response Surface Methodology: Process and Product in Optimization Using Designed Experiments
FinFET SRAM " Device and Circuit Design Considerations
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
IEEE Transactions on Nanotechnology
A Comparative Study of Electrical Characteristic on Sub-10-nm Double-Gate MOSFETs
IEEE Transactions on Nanotechnology
A study on global and local optimization techniques for TCAD analysis tasks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We in this paper for the first time explore the static noise margin (SNM) of a six-transistor (6T) static random access memory (SRAM) cell with nanoscale silicon-on-insulator (SOI) fin-typed field effect transistors (FinFETs). The SNM is calculated with respect to the supply voltage, operating temperature, and cell ratio by performing a three-dimensional mixed-mode simulation. To include the quantum mechanical effect, the density-gradient equation is simultaneously solved in the coupled device and circuit equations. The standard deviation (驴SNM) of SNM versus device's channel length is computed, based upon the design of experiment and response surface methodology. Compared with the result of SNM for SRAM with 32nm planar metal-oxide-semiconductor field effect transistors, SRAM with SOI FinFETs quantitatively exhibits higher SNM and lower 驴SNM. Improvement of characteristics resulting from good channel controllability implies that SRAM cells fabricated with FinFETs continuously maintains cell stability in sub-32nm technology nodes.