SOI digital CMOS VLSI—a design perspective
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
SOI technology and tools (abstract only)
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Body-voltage estimation in digital PD-SOI circuits and its application to static timing analysis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
SOI circuit design concepts
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Leakage-and crosstalk-aware bus encoding for total power reduction
Proceedings of the 41st annual Design Automation Conference
Approaches to run-time and standby mode leakage reduction in global buses
Proceedings of the 2004 international symposium on Low power electronics and design
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient surface-based low-power buffer insertion algorithm
Proceedings of the 2005 international symposium on Physical design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Gate sizing: finFETs vs 32nm bulk MOSFETs
Proceedings of the 43rd annual Design Automation Conference
Design and CAD challenges in 45nm CMOS and beyond
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Yield prediction for 3D capacitive interconnections
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A robust edge encoding technique for energy-efficient multi-cycle interconnect
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Enhanced leakage reduction techniques using intermediate strength power gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Electro-thermal analysis of multi-fin devices
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Low-power FinFET circuit synthesis using multiple supply and threshold voltages
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Is 3D chip technology the next growth engine for performance improvement?
IBM Journal of Research and Development
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus encoding for total power reduction using a leakage-aware buffer configuration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses design challenges of scaled CMOS circuits insub-90nm technologies for high-performance digital applications.To continue scaling of the CMOS devices deep into sub-90nm tech-nologies,fully depleted SOI, strained-Si on SiGe, FinFETs withdouble gate, and even further, three-dimensional circuits will be uti-lizedto design high-performance circuits. We will discuss uniquedesign aspects and issues resulting from this scaling such as gate-to-body tunneling, self-heating, reliability issues, and process vari-ations.As the scaling approaches various physical limits, new SOIdesign issues such as Vt modulation due to leakage, low-voltageimpact ionization, and higher V{t,lin} to maintain adequate V{t,sat},continue to surface.With an eye towards the future, design andCAD issues related to sub-65nm device structures such as doublegate FinFET will be discussed.