Scaling of stack effect and its application for leakage reduction
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Parameterized RTL power models for soft macros
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Leakage control with efficient use of transistor stacks in single threshold CMOS
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Maximum Leakage Power Estimation for CMOS Circuits
VOLTA '99 Proceedings of the IEEE Alessandro Volta Memorial Workshop on Low-Power Design
Full chip leakage estimation considering power supply and temperature variations
Proceedings of the 2003 international symposium on Low power electronics and design
Design and CAD Challenges in sub-90nm CMOS Technologies
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Challenges and design choices in nanoscale CMOS
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Cell Processor Low-Power Design Methodology
IEEE Micro
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
Proceedings of the 2006 international symposium on Low power electronics and design
Leakage power analysis and reduction during behavioral synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level power modeling, estimation, and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A low-latency modular switch for CMP systems
Microprocessors & Microsystems
| Hi-index | 0.00 |
With the advent of nanoscale technologies, developing power efficient ASICs increasingly requires consideration of static power. An effective approach to make RTL synthesis algorithms and tools leakage-aware consists of the smart inference of RTL macros based on design constraints and optimization directives. This involves exploring the new trade-offs spanned by the design of RTL functional units, as an effect of the features of nanoscale technologies and ofthe power optimizations performed by commercial synthesis tools. This work explores these new trade-offs and proves that making RTL macro selection strategies aware of them results in power savings as high as 43%.