Hybrid dual-threshold design techniques for high-performance processors with low-power features
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed-Vth (MVT) CMOS circuit design methodology for low power applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A system level memory power optimization technique using multiple supply and threshold voltages
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
An Investigation of Power Delay Tradeoffs for Dual Vt CMOS Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Proceedings of the 2003 international symposium on Low power electronics and design
Leakage in nano-scale technologies: mechanisms, impact and design considerations
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
Temperature-aware global placement
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Low power gate-level design with mixed-Vth (MVT) techniques
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Achieving continuous VT performance in a dual VT process
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Proceedings of the 2007 international symposium on Physical design
An efficent clustering algorithm for low power clock tree synthesis
Proceedings of the 2007 international symposium on Physical design
High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective
Journal of Systems Architecture: the EUROMICRO Journal
Digital Circuit Optimization via Geometric Programming
Operations Research
Power-optimal RTL arithmetic unit soft-macro selection strategy for leakage-sensitive technologies
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Minimizing leakage: what if every gate could have its individual threshold voltage?
AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications
Device-aware yield-centric dual-Vt design under parameter variations in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Minimizing leakage power in sequential circuits by using mixed Vt flip-flops
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Proceedings of the 13th international symposium on Low power electronics and design
Dual-threshold pass-transistor logic design
Proceedings of the 19th ACM Great Lakes symposium on VLSI
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Low-power design techniques for scaled technologies
Integration, the VLSI Journal - Special issue: Low-power design techniques
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Impact of local interconnects on timing and power in a high performance microprocessor
Proceedings of the 19th international symposium on Physical design
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Biologically-Inspired optimization of circuit performance and leakage: a comparative study
ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
Improving dual Vt technology by simultaneous gate sizing and mechanical stress optimization
Proceedings of the International Conference on Computer-Aided Design
Journal of Electrical and Computer Engineering - Special issue on ESL Design Methodology
Proceedings of the Conference on Design, Automation and Test in Europe
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We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.