Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Static power optimization of deep submicron CMOS circuits for dual VT technology
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
RT-Level ITC'99 Benchmarks and First ATPG Results
IEEE Design & Test
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Design and implementation of the POWER5™ microprocessor
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reverse-body bias and supply collapse for low effective standby power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Delay modeling and static timing analysis for MTCMOS circuits
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Physical design methodology of power gating circuits for standard-cell-based design
Proceedings of the 43rd annual Design Automation Conference
Design for Manufacturability and Yield for Nano-Scale CMOS
Design for Manufacturability and Yield for Nano-Scale CMOS
Lookup Table-Based Adaptive Body Biasing of Multiple Macros
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Skewed flip-flop transformation for minimizing leakage in sequential circuits
Proceedings of the 44th annual Design Automation Conference
Gate-length biasing for runtime-leakage control
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The current use of multi-Vt to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply multi-Vt to flip-flops, but few can take advantage of high-Vt, which causes abrupt changes in timing. We combine low- and high-Vt at the transistor level to design mixed-Vt flip-flops with reduced leakage, an unchanged footprint, and a small increase in either setup time or clock-to-Q delay, but not both. An allocation algorithm for two Vts determines the Vt (mixed, high, or low) of each flip-flop and the Vt of each combinational gate (high or low) in a sequential circuit. Experiments with 65-nm technology show an average leakage saving of 42% compared to conventional multi-Vt approaches; the leakage of flip-flops alone is cut by 78%. This saving is largely unaffected by die-to-die or within-die process variations, which we show through simulations. Standard deviation of leakage caused by process variation is also reduced due to less use of low-Vt devices. We also extend our approach to three Vts, and obtain a further 14% reduction in leakage.