Physics of semiconductor devices
Physics of semiconductor devices
Intrinsic MOSFET parameter fluctuations due to random dopant placement
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Design Challenges of Technology Scaling
IEEE Micro
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Statistical analysis of subthreshold leakage current for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
STAC: statistical timing analysis with correlation
Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Proceedings of the 2004 international symposium on Low power electronics and design
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Physically unclonable functions: manufacturing variability as an unclonable device identifier
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
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Dual-Vt design technique has proven to be extremely effective in reducing subthreshold leakage in both active and standby mode of operation of a circuit in submicrometer technologies. However, aggressive scaling of technology results in different leakage components (subthreshold, gate and junction tunneling) to become significant portion of total power dissipation in CMOS circuits. High-Vt devices are expected to have high junction tunneling current (due to stronger halo doping) compared to low-Vt devices, which in the worst case can increase the total leakage in dual-Vt design. Moreover, process parameter variations (and in turn Vt variations) are expected to be significantly high in sub-50-nm technology regime, which can severely affect the yield. In this paper, we propose a device aware simultaneous sizing and dual-Vt design methodology that considers each component of leakage and the impact of process variation (on both delay and leakage power) to minimize the total leakage while ensuring a target yield. Our results show that conventional dual-Vt design can overestimate leakage savings by 36% while incurring 17% average yield loss in 50-nm predictive technology. The proposed scheme results in 10%-20% extra leakage power savings compared to conventional dual-Vt design, while ensuring target yield: This paper also shows that nonscalability of the present way of realizing high-Vt devices results in negligible power savings beyond 25-nm technology. Hence, different dual-Vt process options, such as metal gate work function engineering, are required to realize high-performance and low-leakage dual-Vt designs in future technologies.