An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques

Authors:
Lara D. Oliver;Krishnendu Chakrabarty;Hisham Z. Massoud
Affiliations:
Duke University, Durham, NC;Duke University, Durham, NC;Duke University, Durham, NC
Venue:
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Year:
2006

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Abstract

We evaluate the effectiveness of dual-Vt design in the presence of both subthreshold leakage and leakage due to gate oxide tunneling. At the device level, we use detailed HSPICE simulation to investigate the total leakage impact of three methods of dual-Vt implementation: multiple channel doping, channel length, and oxide thickness. At the system level, we generate and characterize a standard cell library and apply three representative delay-constrained leakage minimization dual-Vt assignment algorithms to the ISCAS'85 combinational benchmark circuits. Results show that oxide thickness modulation effectively reduces total leakage power consumption, but channel doping and channel length modulation are less effective.