Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Circuit-level techniques to control gate leakage for sub-100nm CMOS
Proceedings of the 2002 international symposium on Low power electronics and design
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Design Techniques for Gate-Leakage Reduction in CMOS Circuits
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 2004 international symposium on Low power electronics and design
Leakage minimization of nano-scale circuits in the presence of systematic and random variations
Proceedings of the 42nd annual Design Automation Conference
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
LOTUS: Leakage Optimization under Timing Uncertainty for Standard-cell designs
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Statistical technology mapping for parametric yield
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Total Power Optimization for Combinational Logic Using Genetic Algorithms
Journal of Signal Processing Systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Standby leakage current minimization is a pressing concern for mobile applications that rely on standby modes to extend battery life. Also, gate oxide leakage current (Igate) has become comparable to subthreshold leakage (Isub) in 90nm technologies. In this paper, we propose a new method that uses a combined approach of sleep-state, threshold voltage (Vt and gate oxide thickness (Tox) assignments in a dual-Vt and dual-Tox process to minimize both Isub and Igate. Using this method, total leakage current can be dramatically reduced since in a known state in standby mode, only certain transistors are responsible for leakage current and need to be considered for high-Vt or thick-Tox assignment. We formulate the optimization problem for simultaneous state, Vt and Tox assignments under delay constraints and propose two practical heuristics. We implemented and tested the proposed methods on a set of synthesized benchmark circuits. Results show an average leakage current reduction of 5-6Xand 2-3X compared to previous approaches that only use state or state+Vt assignment, respectively, with small delay penalties.