Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static leakage reduction through simultaneous threshold voltage and state assignment
Proceedings of the 40th annual Design Automation Conference
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Tutorial 2: Leakage Issues in IC Design: Trends, Estimation, and Avoidance
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Logic synthesis for reducing leakage power consumption under workload uncertainty
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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With process scaling runtime leakage current, when the circuit is operating, has become a major concern in addition to traditional standby mode leakage. In this paper we propose a new leakage reduction method that specifically targets runtime leakage current. We first observe that the state probabilities of nodes in a circuit tend to be skewed, meaning that they have either a high or a low value. We then propose a method that exploits these skewed state probabilities by setting only those transistors to high-Vt (thick-oxide) that have a high likelihood of being OFF (ON) and hence contributing significantly to the total runtime leakage. Accordingly, we also propose a library specifically tailored for the proposed approach, where Vt and Tox assignment with favorably trade-offs under skewed input probabilities are provided. The optimization algorithm performs simultaneous sizing, Vt and Tox assignment and shows substantial leakage improvement over probability-unaware optimization.