Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis and minimization techniques for total leakage considering gate oxide leakage
Proceedings of the 40th annual Design Automation Conference
Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Gate oxide leakage current analysis and reduction for VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Selective gate-length biasing for cost-effective runtime leakage control
Proceedings of the 41st annual Design Automation Conference
Tradeoffs between date oxide leakage and delay for dual Tox circuits
Proceedings of the 41st annual Design Automation Conference
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational Circuits
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Runtime leakage minimization through probability-aware dual-Vt or dual-tox assignment
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Gain-based technology mapping for minimum runtime leakage under input vector uncertainty
Proceedings of the 43rd annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Logic synthesis for reducing leakage power consumption under workload uncertainty
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
Dynamically pulsed MTCMOS with bus encoding for reduction of total power and crosstalk noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Gate oxide leakage and delay tradeoffs for dual-toxcircuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Runtime leakage minimization through probability-aware optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power scan design using first-level supply gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A study on factors influencing power consumption in multithreaded and multicore CPUs
WSEAS Transactions on Computers
An optimization mechanism intended for static power reduction using dual-Vth technique
Journal of Electrical and Computer Engineering
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We propose a new method that uses a combined approach of sleep-state assignment and threshold voltage (Vt) assignment in a dual-Vt process. While each of these methods has previously been used individually, their combined effect has not been leveraged to date. By combining Vt and sleep-state assignment, leakage current can be dramatically reduced since the circuit is in a known state in standby-mode and only transistors that are off need to be considered for high-Vt assignment. A significant improvement in the leakage/ performance trade-off is therefore achievable using such a combined method. We formulate the optimization problem for simultaneous state and Vt assignment under delay constraints and propose both an exact method for its optimal solution as well as a number of practical heuristics with reasonable run time. We compare our results with Vt and sleep state assignment only and demonstrate an average decrease in leakage current of 3.5X compared to previous approaches.