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Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
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Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization
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Parametric yield estimation considering leakage variability
Proceedings of the 41st annual Design Automation Conference
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Proceedings of the 41st annual Design Automation Conference
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
Proceedings of the 41st annual Design Automation Conference
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Variability driven gate sizing for binning yield optimization
Proceedings of the 43rd annual Design Automation Conference
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Proceedings of the 2006 international symposium on Low power electronics and design
Variability-driven formulation for simultaneous gate sizing and post-silicon tunability allocation
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Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Variability driven gate sizing for binning yield optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On the futility of statistical power optimization
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Efficient additive statistical leakage estimation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Evaluating statistical power optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents a novel gate sizing methodology to minimize the leakage power in the presence of process variations. The leakage and delay are modeled as posynomials functions to formulate a geometric programming problem. The existing statistical leakage model of [18] is extended to include the variations in gate sizes as well as systematic variations. We propose techniques to efficiently evaluate constraints on the α-percentile of the path delays without enumerating the paths in the circuit. The complexity of evaluating the objectivefunction is O(|N|2) and that of evaluating the delay constraints is O(|N| + |E|) for a circuit with |N| gates and |E| wires. The optimization problem is then solved using a convex optimization algorithm that gives an exact solution.