Efficient additive statistical leakage estimation

  • Authors:
  • Lerong Cheng;Puneet Gupta;Lei He

  • Affiliations:
  • University of California at Los Angeles, Los Angeles, CA;University of California at Los Angeles, Los Angeles, CA;University of California at Los Angeles, Los Angeles, CA

  • Venue:
  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  • Year:
  • 2009

Quantified Score

Hi-index 0.03

Visualization

Abstract

Nominal power estimation is quick but gives minimal information. Statistical power analysis can provide information on yield, chip robustness, etc., but current methods are unnecessarily slow and complex. This is primarily because existing leakage-power models, which model leakage power as lognormal distribution and calculate chip leakage power based on Wilkinson's approach, are not directly additive. Hence, for each incremental change of the circuit, the covariances between each pair of circuit elements need to be recalculated, which is inefficient. In this paper, we proposed a simple additive polynomial leakage-variation model. With additivity, we can calculate chip leakage power and leakage power after incremental change very efficiently. Experimental results show that our method is five times faster than the existing Wilkinson's approach while having no accuracy loss in mean estimation and about 1% accuracy loss in standard-deviation and 99%-percentile-point estimations.