Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages
Proceedings of the 42nd annual Design Automation Conference
Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Thermal-induced leakage power optimization by redundant resource allocation
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
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Leakage current is a key factor in IC power consumption even in the active operating mode. We investigate the simultaneous optimization of gate size and threshold voltage to reduce leakage power. We assume a standard-cell-based design flow where the available cell sizes and threshold voltages (V{t}'s) are given, and model the optimization as a mixed-integer linear programming (MLP) problem. In addition to the exact model, two faster approximate MLP models are proposed, along with CAD tools that generate the models automatically. We present experimental results which show that optimal designs derived from the exact MLP model can achieve the same performance as all-low-V{t} unit-size designs, but with only one third the leakage power. The approximate MLP models can be solved about 25 times faster than the optimal model with negligible errors. All the proposed models can be extended to take dynamic power and multiple supply voltages into consideration.