Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages

Authors:
Feng Gao;John P. Hayes
Affiliations:
University of Michigan, Ann Arbor, MI;University of Michigan, Ann Arbor, MI
Venue:
Proceedings of the 42nd annual Design Automation Conference
Year:
2005

Citing 10
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Abstract

Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt's are common ways to meet power and timing budgets. We propose an automatic implementation of both these techniques using a mixedinteger linear programming model called MLP-exact, which minimizes a circuit's total active-mode power consumption. Unlike previous linear programming methods which only consider local optimality, MLP-exact, can find a true global optimum. An efficient, non-optimal way to solve the MLP model, called MLP-fast,, is also described. We present a set of benchmark experiments which show that MLP-fast, is much faster than MLP-exact,, while obtaining designs with only slightly higher power consumption. Furthermore, the designs generated by MLP-fast, consume 30% less power than those obtained by conventional, sensitivity-based methods.