Proceedings of the 39th annual Design Automation Conference
Low Power Solution for Wireless Applications
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Switching-activity driven gate sizing and Vth assignment for low power design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Technology mapping for low leakage power and high speed with hot-carrier effect consideration
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have proposed a new algorithm to realize dual threshold CMOS circuits. Our algorithm produces significantly better results for the ISCAS benchmark circuits compared to the reported results.