Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Performance optimization using separator sets
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
VLSID '01 Proceedings of the The 14th International Conference on VLSI Design (VLSID '01)
Proceedings of the 2003 international symposium on Low power electronics and design
Low power design using dual threshold voltage
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Optimal voltage assignment approach for low power using ILP
WSEAS Transactions on Circuits and Systems
A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller Cost
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Optimal dual voltage assignment algorithm for low power under timing-constraints
ICC'08 Proceedings of the 12th WSEAS international conference on Circuits
Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
| Hi-index | 0.00 |
Power consumption has gained much saliency in circuit design recently. One design problem is modelled as "Under a timing constraint, to minimize power as much as possible". Previous research regarding this problem focused on either minimizing dynamic power by gate sizing, or reducing leakage power by dual threshold voltage assignment on non-critical path. However, given a timing constraint, an optimization algorithm must be able to utilize gate sizing and threshold-voltage assignment inter-changeably, in order to minimize total power consumption including dynamic and leakage power in active mode and leakage power in idle mode. We find that switching-activity of a gate plays an important role in making decision as to choosing gate sizing or threshold-voltage assignment for performance improvement. For high switching-activity gates, threshold-voltage assignment should be used while for low switching-activity gates, gate sizing should be utilized. We develop an algorithm to perform gate sizing and threshold-voltage assignment simultaneously taking switching activity into consideration. The results show that under the same timing constraint, our circuits have 16.26%, and 18.53%, improvement of total power as compared to the original circuits for the cases where the percentage of active time are 100%, and 50%, respectively.