Low power synthesis of dual threshold voltage CMOS VLSI circuits

A static power model for architects

Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture

Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors

Proceedings of the 39th annual Design Automation Conference

Logic synthesis for low power

Logic Synthesis and Verification

Standby power optimization via transistor sizing and dual threshold voltage assignment

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Energy-efficient skewed static logic with dual Vt: design and synthesis

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)

Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits

ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference

High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

Design methodology for fine-grained leakage control in MTCMOS

Proceedings of the 2003 international symposium on Low power electronics and design

Simultaneous Vt selection and assignment for leakage optimization

Proceedings of the 2003 international symposium on Low power electronics and design

Coupling delay optimization by temporal decorrelation using dual threshold voltage technique

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power

LECTOR: a technique for leakage reduction in CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Selective gate-length biasing for cost-effective runtime leakage control

Proceedings of the 41st annual Design Automation Conference

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design

Low power design using dual threshold voltage

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Low power gate-level design with mixed-Vth (MVT) techniques

SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design

Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths

ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design

Low-power fanout optimization using multiple threshold voltage inverters

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Probabilistic dual-Vth leakage optimization under variability

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

Total leakage power optimization with improved mixed gates

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case Study

ICCD '05 Proceedings of the 2005 International Conference on Computer Design

Switching-activity driven gate sizing and Vth assignment for low power design

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Technology mapping for low leakage power and high speed with hot-carrier effect consideration

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Probabilistic evaluation of solutions in variability-driven optimization

Proceedings of the 2006 international symposium on Physical design

Discrete Vt assignment and gate sizing using a self-snapping continuous formulation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Design of mixed gates for leakage reduction

Proceedings of the 17th ACM Great Lakes symposium on VLSI

Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors

Proceedings of the 2007 international symposium on Physical design

High-speed, low-leakage integrated circuits: An evolutionary algorithm perspective

Journal of Systems Architecture: the EUROMICRO Journal

Minimizing leakage: what if every gate could have its individual threshold voltage?

AIAP'07 Proceedings of the 25th conference on Proceedings of the 25th IASTED International Multi-Conference: artificial intelligence and applications

A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing

Proceedings of the 13th international symposium on Low power electronics and design

A new algorithm for simultaneous gate sizing and threshold voltage assignment

Proceedings of the 2009 international symposium on Physical design

The epsilon-approximation to discrete VT assignment for leakage power minimization

Proceedings of the 2009 International Conference on Computer-Aided Design

A new algorithm for simultaneous gate sizing and threshold voltage assignment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment

Proceedings of the 2010 Asia and South Pacific Design Automation Conference

Lagrangian relaxation for gate implementation selection

Proceedings of the 2011 international symposium on Physical design

Simultaneous Vtselection and assignment for leakage optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits

Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI

Biologically-Inspired optimization of circuit performance and leakage: a comparative study

ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems