Simultaneous Vtselection and assignment for leakage optimization

Authors:
Vishal Khandel wal;Azadeh Davoodi;Ankur Srivastava
Affiliations:
University of Maryland, College Park, MD;University of Maryland, College Park, MD;University of Maryland, College Park, MD
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2005

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Abstract

This paper presents a novel approach for leakage optimization through simultaneous Vt selection and assignment. Vt selection implies deciding the right value for Vt and assignment implies deciding which gates should be assigned a particular threshold voltage. We also include the effect of variability in threshold voltage on delay and leakage due to fabrication process variations in our formulations and present a scheme that lets the designer control the leakage and delay variability in his design. The proposed algorithm is a general mathematical formulation that has been shown to trivially extend to multiple threshold voltages.