Stress aware switching activity driven low power design of critical paths in nanoscale CMOS circuits

Authors:
Sudarshan Srinivasan;Bharath Phanibhushana;Arunkumar Vijayakumar;Sandip Kundu
Affiliations:
University of Massachusetts Amherst, Amherst, MA, USA;University of Massachusetts Amherst, Amherst, MA, USA;University of Massachusetts Amherst, Amherst, MA, USA;University of Massachusetts Amherst, Amherst, MA, USA
Venue:
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Year:
2011

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Abstract

Recent research on low power circuits make use of dual VT and strained silicon technologies. Low VT assignment on performance critical paths improves performance at the expense of leakage current. Strained silicon devices on the other hand have greater leakage but provide much larger ON current. The increased drive strength can be used to reduce gate sizes. In this work we show that selective use of strained silicon gates in high-activity critical paths reduce overall power due to decreased dynamic power arising from smaller gate sizes, that more than offset increased leakage due to strained silicon gate. Similarly, we find that up-sizing gates in low-activity critical paths reduce total power. Even though up-sized gates dissipate more dynamic power, lower switching activity, coupled with lower leakage compared to low VT devices make this a better choice. An optimization algorithm based on slack distribution between low and high switching activity gates is presented. Simulation results show an overall power benefit of 5.4% while improving performance by 15% even though overall leakage is 1% higher than original circuit.