Design and optimization of low voltage high performance dual threshold CMOS circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Simultaneous Vt selection and assignment for leakage optimization
Proceedings of the 2003 international symposium on Low power electronics and design
Proceedings of the 2003 international symposium on Low power electronics and design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Minimizing total power by simultaneous Vdd/Vth assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 13th international symposium on Low power electronics and design
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A common concern as we scale down transistor threshold voltages while migrating to new process technologies is the requirement to achieve timing closure within a given power budget over various process corners. High performance microprocessors are designed keeping in mind the various process technologies, application space and multi-site fabrication requirements. Described here is an optimization methodology and a unique topology-aware heuristic algorithm employed for high speed microprocessor designs capable of simultaneous threshold voltage selection for library cells across various technology process corners. The algorithm uses knowledge of the circuit topology rather than considering only the immediate local connectivity as is suggested in other heuristic methods and evaluates timing criticalities originating from different input and output logic cones associated with every pin of a failing path. The VTH selection is done so as to affect multiple failing paths with each low VTH cell selection, hence reducing leakage power. Two sets of algorithms are used alternately. One takes advantage of the circuit topology to address multiple failing paths simultaneously. The other performs a fine tuned optimization that has more granularity while considering a particular failing path. This flow is not limited to dual threshold VTH selection but can also support the use of multi-VTH library cells. This flow and its algorithms reduced the usage of low VTH in a particular multi-million transistor design from 35.3% to 10.7% without any loss of performance thus resulting in a 55.6% drop in leakage power. Reducing the usage of lower VTH cells results in significant power reduction. This reduction in power could also allow running the chip at a higher VDD and frequency within the original power envelope. Production results from this tool exceeded the optimization efforts of another commercially used EDA optimization tool.