Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 39th annual Design Automation Conference
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Large-scale nonlinear optimization in circuit tuning
Future Generation Computer Systems
Proceedings of the 2007 international symposium on Physical design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
The epsilon-approximation to discrete VT assignment for leakage power minimization
Proceedings of the 2009 International Conference on Computer-Aided Design
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
Post-synthesis leakage power minimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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We propose a parallel and randomized algorithm to solve the problem of discrete dual-Vt assignment combined with continuous gate sizing which is an important low power design technique in high performance domains. This combinatorial optimization problem is particularly difficult to solve on large-sized circuits. We first introduce a hybrid algorithm which combines the existing heuristics and convex formulations for this problem to achieve a better tradeoff between the runtime of the algorithm and the quality of generated solution. We then extend our algorithm to include parallelism and randomization. We introduce a unique utilization of parallelism to better identify the optimization direction. Consequently, we can reduce both the number of iterations in optimization as well as improve the quality of solution. We further use random sampling to avoid being trapped in local minima and to focus the optimization effort on the more "promising" regions of the solution space. Our algorithm improves the average power by 37% compared to an approach which is based on solving a continuous convex program and applying discretization. Power improvement is over 50% for larger benchmarks for an implementation on a grid of 9 computers.