Minimizing total power by simultaneous Vdd/Vth assignment

Authors:
A. Srivastava;D. Sylvester
Affiliations:
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

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Abstract

In this paper, we investigate the effectiveness of simultaneous multiple supply and threshold voltage assignment in minimizing the total power (static+dynamic) in generic digital CMOS designs. Achievable power reductions under varying conditions are investigated, including static-power limited designs and sub-1-V processes. Rules-of-thumb are developed for optimal Vdd's and Vth's to be used in future designs. These models show the optimal second Vdd to be approximately half the nominal Vdd while the potential total power savings is significantly greater than previously anticipated (60%-65%). We describe the impact of level conversion delays and also demonstrate that the scaling properties of multivoltage systems are very good, particularly when considering impending device scaling advancements.