Energy-efficient skewed static logic with dual Vt: design and synthesis

Authors:
Chulwoo Kim;Ki-Wook Kim;Sung-Mo Kang
Affiliations:
Department of Electronics and Computer Engineering, Korea University, Seoul 136-701, Republic of Korea;Brocade Communications Systems, Inc. San Jose, CA;Baskin School of Engineering, University of California, Santa Cruz, CA
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Year:
2003

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Abstract

In this paper, we describe skewed static logic (S2L) with topology-dependent dual Vt which exhibits an energy-efficient operation. S2L consumes less dynamic and static power compared to monotonic static (MS) CMOS. Speed degradation of S2L, if any, can be offset by an accelerator circuit. We have designed NAND-NOR gate chains using 0.18-µm CMOS technology and verified that S2L reduces energy-delay product over MS CMOS by 27%-50%. We have also designed 32-b carry-lookahead adders and verified that S2L with dual Vt reduces delay by 43% and energy-delay productby 31% for 1-V power supply over conventional CMOS circuit. Synthesis algorithm for S2L is developed and the experimental results show S2L consumes 23% less power than MS CMOS with minor increase in delay.