Optimal voltage assignment approach for low power using ILP

Authors:
Yu-Cheng Lin;Hsin-Hsiung Huang;Cheng-Chiang Lin;Tsai-Ming Hsieh
Affiliations:
Dept. of Information and Electronic Commerce, Kainan University, Taoyuan, Taiwan;Institute of Electronic Engineering, Lunghwa Univ. of Science and Technology, Taoyuan, Taiwan;Dept. of Information and Computer Engineering, Chung Yuan Christian University, Chung-Li, Taiwan;Dept. of Information and Computer Engineering, Chung Yuan Christian University, Chung-Li, Taiwan
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2008

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Abstract

In this paper, we proposed an optimal voltage assignment approach which determines the proper voltage for each gate in the gate level netlist using dual supply voltages. To the best of our knowledge, it is the first work to integrate the impact of the level shifters into the integer linear programming (ILP) formulations. The objective of the paper is to minimize the total power, including the gates and the level shifters, under the given delay constraints. For the gate level netlist, the voltage assignment approach, which determines the delay for gates and wires and the power for the gates and level shifters, is proposed. To reduce the runtime for the ILP constraints, we also propose the node-based concept to formulate the timing constraints. Finally, we optimally assign the voltages for all gates. The ILP formulations are solved by using the ILP solver (LINGO 10.0) and the experimental results with ISCAS circuits indicate the significant improvement on total power using the dual supply voltages.