Principles of CMOS VLSI design: a systems perspective
Principles of CMOS VLSI design: a systems perspective
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Life is CMOS: why chase the life after?
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Standby power optimization via transistor sizing and dual threshold voltage assignment
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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In this paper, we present a novel approach to obtain any desired intermediate threshold voltage in a dual VT process. The intermediate threshold voltages are achieved by combining low and high threshold voltages in a device. We show that this combination can be easily implemented in layouts with negligible design and manufacturing overhead. Our results show that power-delay characteristics of the achieved intermediate thresholds match well with the ideal (but impractical) scenario that assumes that all intermediate thresholds are available in the technology.