Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Proceedings of the 39th annual Design Automation Conference
A Practical Transistor-Level Dual Threshold Voltage Assignment Methodology
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Defocus-aware leakage estimation and control
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Impact of Gate-Length Biasing on Threshold-Voltage Selection
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Full-chip model for leakage-current estimation considering within-die correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
Microelectronics Journal
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
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The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickness are scaled. Consequently, the identification of different leakage components is very important for estimation and reduction of leakage. Moreover, the increasing statistical variation in the process parameters has led to significant variation in the transistor leakage current across and within different dies. Designing with the worst case leakage may cause excessive guard-banding, resulting in a lower performance. This paper explores various intrinsic leakage mechanisms including weak inversion, gate-oxide tunneling and junction leakage etc. Various circuit level techniques to reduce leakage energy and their design trade-off are discussed. We also explore process variation compensating techniques to reduce delay and leakage spread, while meeting power constraint and yield.