Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Electrothermal analysis of VLSI systems
Electrothermal analysis of VLSI systems
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Temperature-aware microarchitecture
Proceedings of the 30th annual international symposium on Computer architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Static energy reduction techniques for microprocessor caches
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Circuit and microarchitectural techniques for reducing cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage in nano-scale technologies: mechanisms, impact and design considerations
Proceedings of the 41st annual Design Automation Conference
System level leakage reduction considering the interdependence of temperature and leakage
Proceedings of the 41st annual Design Automation Conference
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Efficient full-chip thermal modeling and analysis
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Adaptive multi-domain thermal modeling and analysis for integrated circuit synthesis and design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Temperature-aware register reallocation for register file power-density minimization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reducing functional unit power consumption and its variation using leakage sensors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Leakage power consists of an increasing portion of the total power consumption for modern IC designs. Due to the strong inter-dependency between leakage and temperature, it becomes imperative to consider the thermal effects while optimizing the leakage power. In this paper we present a temperaturedependent optimization methodology for on-chip caches. By integrating fast yet accurate coupled thermal-leakage simulations into an optimization flow, we are able to optimally tradeoff between the cache performance and leakage power while considering realistic on-chip temperature distribution. Our analysis indicates that for future memory intensive designs, the lack of chip temperature information can cause a significant error in the leakage power estimation, thus leading to non-optimal cache designs. Our results further imply that the optimization of cache performance and leakage power shall be attacked as part of the whole system design task in which chip-level floorplanning and its thermal impacts are fully addressed.