A low power SRAM using auto-backgate-controlled MT-CMOS
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Analysis of dual-Vt SRAM cells with full-swing single-ended bit line sensing for on-chip cache
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Adaptive Mode Control: A Static-Power-Efficient Cache Design
Proceedings of the 2001 International Conference on Parallel Architectures and Compilation Techniques
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
HPCA '01 Proceedings of the 7th International Symposium on High-Performance Computer Architecture
Total leakage optimization strategies for multi-level caches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Temperature-Dependent Optimization of Cache Leakage Power Dissipation
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-leakage robust SRAM cell design for sub-100nm technologies
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Reducing Data Cache Susceptibility to Soft Errors
IEEE Transactions on Dependable and Secure Computing
Case study of reliability-aware and low-power design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating the effects of cache redundancy on profit
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Compiler-guided leakage optimization for banked scratch-pad memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Quantitative analysis and optimization techniques for on-chip cache leakage power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
DESC: energy-efficient data exchange using synchronized counters
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
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On-chip L1 and L2 caches represent a sizeable fraction of the totalpower consumption of microprocessors. In deep sub-micron technology,the subthreshold leakage power is becoming the dominantfraction of the total power consumption of those caches. In thispaper, we present optimization techniques to reduce the leakagepower of on-chip caches assuming that there are multiple thresholdvoltages, VTH's, available. First, we show a cache leakage optimizationtechnique that examines the trade-off between access timeand leakage power by assigning distinct VTH's to each of the fourmain cache components - address bus drivers, data bus drivers,decoders, and SRAM cell arrays with sense-amps. Second, we showoptimization techniques to reduce the leakage power of L1 and L2on-chip caches without affecting the average memory access time.The key results are: 1) 2 VTH's are enough to minimize leakage in asingle cache; 2) if L1 size is fixed, increasing the L2 size can resultin much lower leakage without reducing average memory accesstime; 3) if L2 size is fixed, reducing L1 size can result in lower leakagewithout loss of the average memory access time; and 4) smallerL1 and larger L2 caches than are typical in today's processorsresult in significant leakage and dynamic power reduction withoutaffecting the average memory access time.