Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

Authors:
Christophe Giacomotto;Mandeep Singh;Milena Vratonjic;Vojin G. Oklobdzija
Affiliations:
Advanced Computer systems Engineering Laboratory, University of California, Davis, Davis, USA CA 95616;Advanced Computer systems Engineering Laboratory, University of California, Davis, Davis, USA CA 95616;Advanced Computer systems Engineering Laboratory, University of California, Davis, Davis, USA CA 95616;Advanced Computer systems Engineering Laboratory, University of California, Davis, Davis, USA CA 95616
Venue:
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Year:
2009

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Abstract

An analysis of the efficiency of power-gating for Clocked Storage Elements (CSEs) is presented. Two CSE topologies: the Transmission Gate Master Slave latch (TGMS) and the Write Port Master Slave latch (WPMS) are examined along with their respective circuits with sleep transistors. In this work, we study the benefits of adding sleep transistors coupled with regular clock-gating during inactive mode. We examine the energy savings for standard clock gated CSEs versus their power gated counterparts. This is done by studying how the leakage energy saved with power gating offsets the energy consumed by the extra transistors added to support it. It is not always beneficial to add sleep transistors when deciding between power-gating or just using clock-gating. We also study how the results and tradeoff change with voltage scaling.