High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)

Performance analysis and design space exploration for high-end biomedical applications: challenges and solutions

CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis

Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

Flip-flop energy/performance versus clock slope and impact on the clock network design

IEEE Transactions on Circuits and Systems Part I: Regular Papers

General strategies to design nanometer flip-flops in the energy-delay space

IEEE Transactions on Circuits and Systems Part I: Regular Papers

Finding the energy efficient curve: gate sizing for minimum power under delay constraints

VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions

Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: part I-methodology and design strategies

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

A new methodology for power-aware transistor sizing: free power recovery (FPR)

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

From energy-delay metrics to constraints on the design of digital circuits

International Journal of Circuit Theory and Applications