Low power, testable dual edge triggered flip-flops
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Proceedings of the 2002 international symposium on Low power electronics and design
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Load-Sensitive Flip-Flop Characterization
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Leakage in Nanometer CMOS Technologies (Series on Integrated Circuits and Systems)
Activity-sensitive flip-flop and latch selection for reduced energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
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In this paper (split into Parts I and II), an extensive comparison of existing flip-flop (FF) classes and topologies is carried out. In contrast to previous works, analysis explicitly accounts for effects that arise in nanometer technologies and affect the energy-delay-area tradeoff (e.g., leakage and the impact of layout and interconnects). Compared to previous papers on FFs comparison, the analysis involves a significantly wider range of FF classes and topologies. In particular, in this Part I, the comparison strategy, which includes the simulation setup, the energy-delay estimation methodology, and an overview of an optimum design strategy, together with the introduction of the analyzed FF classes and topologies, are reported.