Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the 2002 international symposium on Low power electronics and design
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
Low Power Design Essentials
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and comparison on full adder block in submicron technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Estimation of average switching activity in combinational logic circuits using symbolic simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, the adoption of general metrics of the energy-delay tradeoff is investigated to achieve energy-efficient design of digital CMOS very large-scale integrated circuits. Indeed, as shown in a preliminary analysis on the performance of various commercial microprocessors, a wide range of EiDj metrics is typically adopted. Physical interpretation and interesting properties for the designs minimizing EiDj metrics are provided together with the adoption of the Logical Effort theory to define practical design constraints. Two design examples in a 65-nm CMOS technology are also reported to exemplify the theoretical results. Copyright © 2011 John Wiley & Sons, Ltd. (The relation between general metrics of the energy-delay (E-D) tradeoff and the achievement of energy-efficiency in digital CMOS circuits is investigated. Qualitative requirements in terms of Ei Dj products are translated into quantitative results in terms of transistors sizings corresponding to welldefined energy-to-delay sensitivities, while Logical Effort is employed to determine practical design constraints. Two examples in a 65-nm technology are reported to exemplify the design framework. Copyright © 2011 John Wiley & Sons, Ltd.)