A table-based approach to study the impact of process variations on finfet circuit performance
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Brute-force sequential circuits with reduced clock load and simpler circuitry are widely used in the state-of-the-art integrated circuits. In this paper, new brute-force independent-gate FinFET sequential circuits are evaluated for power consumption, speed, and noise immunity characteristics at different process corners under parameter fluctuations in a 32nm FinFET technology. With the independent-gate FinFET latches and flip-flops, the total active mode power consumption, the clock power, and the average leakage power are reduced by up to 47%, 32%, and 37%, respectively, while maintaining similar speed and data stability as compared to the circuits with tied-gate FinFETs across different process corners. Furthermore, the area is reduced by 20% with the new sequential circuits due to the smaller transistors as compared to the circuits with tied-gate FinFETs.