A table-based approach to study the impact of process variations on finfet circuit performance

Authors:
Rajesh A. Thakker;Chaitanya Sathe;Maryam Shojaei Baghini;Mahesh B. Patil
Affiliations:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, University of Illinois, Urbana, IL and Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

This paper presents a novel table-based approach for efficient statistical analysis of Finfield effect transistor circuits. The proposed approach uses a new scheme for interpolation of look-up tables (LUTs) with respect to process parameters. The effect of various process parameters, viz., channel length, fin width, and effective oxide thickness is studied for three circuits: buffer chain, static random access memory cell, and high-gain low-voltage op-amp. Compared to mixed-mode (device-circuit) simulation, the proposed LUT-based approach is shown to be much faster, thus making it practically a feasible and attractive option for variability analysis especially for emerging technologies where compact models are not available for circuit simulation.