A novel table-based approach for design of FinFET circuits

Authors:
Rajesh A. Thakker;Chaitanya Sathe;Angada B. Sachid;Maryam Shojaei Baghini;V. Ramgopal Rao;Mahesh B. Patil
Affiliations:
Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, University of Illinois, Urbana, IL and Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India;Department of Electrical Engineering, Indian Institute of Technology, Bombay, India
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2009

Citing 7
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Abstract

A new lookup-table (LUT) approach, based on normalization of the drain current with an ID-VG template, is proposed for simulation of MOS transistor circuits. The LUT approach is validated by considering two examples and by comparing the LUT results with mixed-mode (device-circuit) simulation results. This approach is implemented in a circuit simulator and integrated, for the first time, with an optimizer to enable efficient design of circuits, particularly those involving novel technologies for which compact models are not fully developed. Three FinFET-based circuits are designed to demonstrate the effectiveness of the proposed environment. Furthermore, it is shown that the table-based platform can take into account variations in process, supply voltage, and temperature during the design.