Vertically integrated SOI circuits for low-power and high-performance applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Double-gate SOI devices for low-power and high-performance applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
SRAM read/write margin enhancements using FinFETs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch
Microelectronics Journal
Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology
Journal of Computational Electronics
Design space exploration of FinFET cache
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively used to improve performance and reduce power in sub-50nm circuits. In this paper, we propose a high-performance sense-amplifier design using independent gate control in symmetric and asymmetric DG devices. The proposed design reduces the sensing delay of the sense amplifier by 30-35% and dynamic power by 10% (at 6GHz) from the connected gate design.