Analysis of double-gate CMOS for double-pole four-throw RF switch design at 45-nm technology

Authors:
Viranjay M. Srivastava;K. S. Yadav;G. Singh
Affiliations:
Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan, India 173234;VLSI Design Group, Central Electronics Engineering Research Institute (CEERI), Pilani, India 333031;Department of Electronics and Communication Engineering, Jaypee University of Information Technology, Solan, India 173234
Venue:
Journal of Computational Electronics
Year:
2011

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Abstract

In this paper, we have analyzed a 45-nm RF CMOS switch design technology with the double-pole four-throw circuit by using independently controlled double-gate MOSFET. The proposed switch reduces the number of transistors and increases the logic density per unit area as compare to the conventional CMOS switch. With the unique independent double-gate properties, we have demonstrated the potential advantages in terms of the drain current, threshold voltage, attenuation with ON resistance, flat-band capacitances, charge density and power dissipation of the proposed switch, which provides a switch with a significant drive circuit that is free from the signal propagation delay and additional voltage power supply. Moreover, the main emphasis is to provide a plurality of such switches arranged in a densely configured switch array, which provides a lesser attenuation, and better isolation with fast switching speed.